Signal termination techniques are, conventionally, used to reduce or prevent a transmitted signal from being reflected from a receiving side toward the transmitting side. Generally, a signal termination technique is provided on a board with a semiconductor device, such as a semiconductor memory device, rather than being provided by the semiconductor device itself. Signal lines are arranged to transmit a signal between devices on the board, and a termination voltage and a termination resistor are arranged at end portions of the signal lines to thereby terminate the signal.
However, as the number of signal lines has increased, it has become difficult to arrange the termination voltage and the termination resistor. As a result, techniques have been introduced that terminate a signal within the device mounted on the board rather than on the board. These techniques may be collectively referred to as on die termination (ODT).
FIG. 1 is a block diagram schematically illustrating a conventional on die termination technique. A memory controller 10 and a memory 20 are provided. The memory 20 includes a command buffer (CB) 22, a command decoder (CD) 24, data input buffers (DIB) 26-1 to 26-n, and on die termination circuits (ODT) 28-1 to 28-n. In FIG. 1, the reference numeral 21 denotes a command input pad(s) for inputting a command, and reference numerals 23-1 to 23-n denote data input pads for inputting data.
The memory controller 10 transmits a command (COM) and data (DA) through command lines com and data lines da. The memory 20 performs a write operation or a read operation in response to the command (COM) input through the command pad(s) 21. The command buffer 22 buffers a command (COM). The command decoder 24 decodes the buffered command output from the command buffer 22 to generate a write command or a read command and an on die termination control signal. Each of the data input buffers 26-1 to 26-n buffer data DA inputted through the data input pads 23-1 to 23-n in response to the on die termination control signal output from the command decoder 24. Each of the on die termination circuits 28-1 to 28-n is enabled in response to the on die termination control signal output from the command decoder 24 to terminate signals inputted through the data input pads 23-1 to 23-n. 
The on die termination technique of FIG. 1 is described with reference to a memory system, however, an on die termination circuit can be arranged on a data input pad (or terminal) of any device having a data input function.
FIG. 2 is a circuit diagram illustrating a conventional on die termination circuit. The on die termination circuit of FIG. 2 includes inverters I1 to I3, a PMOS transistor P1, and an NMOS transistor N1. In FIG. 2, TE denotes an on die termination control signal and reference numeral 23 denotes a data input pad.
In the circuit of FIG. 2, when an on die termination control signal TE of a “low” level is applied, the inverter I2 generates a signal of a “low” level and the inverter I3 generates a signal of a “high” level. Thus, the PMOS transistor P1 and the NMOS transistor N1 are turned off so that the pad 23 goes to a high impedance state. When the die termination control signal TE is at a “high” level, the inverter I2 generates a signal of a “high” level and the inverter I3 generates a signal of a “low” level. Thus, the PMOS transistor P1 and the MOS transistor N1 are turned on, so that the pad 23 has a power voltage VCC/2. Therefore, a signal applied through the pad 23 is terminated to a level of VCC/2.
However, when the on die termination control signal TE is at a “high” level and a signal of a “high” level is applied through the pad 23, the signal of a “high” level applied through the pad 23 is not raised completely to the “high” level. This is because the PMOS transistor P1 and the NMOS transistor N1 are turned on so that a current continually flows through the NMOS transistor N1.
Also, when the on die termination control signal TE is at a “high” level and a signal of a “low” level is applied through the pad 23, the signal of a “low” level applied through the pad 23 does not drop completely to the “low” level. This is because the PMOS transistor P1 and the NMOS transistor N1 are turned on so that a current is continually supplied through the PMOS transistor P1.
The conventional on die termination circuit of FIG. 2 may be advantageous for high speed operation in that a signal applied through the pad 23 does not experience a “full swing” between a power voltage (VCC) and a ground voltage when on die termination is provided but has a disadvantage in that the PMOS transistor and the NMOS transistor are always turned on during on die termination operation so current consumption occurs from the power voltage to the ground voltage, thereby increasing power consumption.
FIG. 3 is a circuit diagram illustrating another conventional on die termination circuit. The on die termination circuit of FIG. 3 includes an inverter I4, a NOR gate NOR1, a NAND gate NA1, a PMOS transistor P2, and an NMOS transistor N2. When an on die termination control signal TE of a “low” level is generated, the NAND gate NA1 generates a signal of a “high” level output. The inverter I4 generates a signal of a “high” level so the NOR gate NOR1 generates a signal of a “low” level. Thus, the PMOS transistor P2 and the NMOS transistor N2 are turned off and on die termination operation is not performed.
When the on die termination control signal TE at a “high” level and a signal of a “high” level is applied through the pad 23, the NAND gate NA1 generates a signal of a “low” level and the PMOS transistor P2 is turned on. The inverter I4 generates a signal of a “low” level and the NOR gate NOR1 generates a signal of a “low” level and the NMOS transistor N2 is turned off. Therefore, the signal of a “high” level applied through the pad 23 is terminated to a power voltage (VCC) level.
When the on die termination control signal TE is at a “high” level and a signal of a “low” level is applied through the pad 23, the NAND gate NA1 generates a signal of a “high” level and the PMOS transistor P2 is turned off. The inverter I4 generates a signal of a “low” level and the NOR gate NOR1 generates a signal of a “high” level and the NMOS transistor N2 is turned on. Therefore, a signal of a “low” level applied through the pad 23 is terminated to a ground voltage level.
The conventional on die termination circuit of FIG. 3, may be advantageous in that either the PMOS transistor or the NMOS transistor is turned on during on die termination and, therefore, current flow does not occur from a power voltage to a ground voltage, thus, potentially decreasing power consumption. However, it may not be appropriate for high speed operation in that a signal applied through the pad experiences a full swing between VCC and ground.